Abstract normal basis multiplier; hardware architecture; domino logic; True

 

 

 

Abstract

A novel VLSI analysis for a finite field multiplier with reordered normal
basis (RNB) is presented in the proposed system. The hardware architecture creates
the use of domino logic building blocks as well as True Single Phase Clock
(TSPC) flip-flops to achieve exceptional presentation. The multiplier has been realized in a 70nm CMOS process and
can execute multiplication correctly upto a clock rate of 1.789 GHz. Compared
to related implementations, the new design yields a 50% reduction in area consumption,
and a 15% increase in maximum operating speed and also less power. The range of the multiplier,
233, is suggested by the National Institute of Standard and Technology (NIST)
for elliptic key cryptography. Finite field multipliers such as the proposed
one have applications in public key cryptography for embarrassed devices such as smart cards or hand held
devices.

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Keywords: VLSI;
Finite field multiplier; reordered normal basis multiplier; hardware architecture;
domino logic; True Single Phase Clock
(TSPC).

1. Introduction

Low power plays an important role in electronics
industry especially in VLSI field (Omnia
S. Fadl et al.,2016; Ahmad Karim et al.,2018,). With the low power utilization,
security is an additional convincing requirement for some applications. For
that finite fields are comprehensively used in
communication systems, mainly for error correcting codes and cryptography (KangquanLi et al., 2016; Atef Ibrahim et.al.,
2017 ;Bahram Rashidi, et.al., 2016; Che Wun
Chiou et.al .,2010; Sun-Mi Park
et al.,2014, Mohamed Asan
Basiri M et al.,2017; Kimmo Jarvinen.,2011, C.
Grabbe, M. Bednara, J. Teich et al.,2003). There
subsist a number of basis for signifying the field elements and performing
arithmetic operations such as multiplication, addition, subtraction and
inversion. Nowadays
need for low power has caused a major pattern shift where power dissipation has
suited as significant consideration as performance and area (Praveen Singh
et al., 2016). Two most
important bases commonly used in practice are the polynomial basis and the
normal basis (Che Wun Chiou et.al., 2010). Polynomial
basis is appropriate for software implementation, while normal basis is
frequently used for hardware implementation; mainly it is suitable for
performing squaring, inverse and exponential process(C. Grabbe
et al;2003).The normal basis provides
improved time-area complexity than existing inverters as with large m(Che Wun
Chiou, et.al., 2010;Bahram
Rashidi et.al.,2016; B. Sunar and
C. K. Koc.,2001)

  The normal basis, the addition of two fundamentals
can be achieved by easy bit-by-bit exclusive-or element coefficients.
Multiplication is more complex, and it can be replicated as a matrix-vector multiplication
(Che
Wun Chiou et.al., 2010).The difficulties of the
multiplication depend on the amount of non-zero elements within the
multiplication matrix, which is referred to as the intricacy of the normal
basis, CN. It has been shown that CN can be uttered as a function of the field
size (m), and is minimized for two classes of fields which are referred to as
type I and II Optimal Normal Basis (ONB) (Sunar and C. K. Koc.,2001).

Type I optimal normal basis is being excluded from many
security standards such as NIST and ANSI because it only survive for non-prime
field sizes. Type II ONB is suggested in various values and is generally used
for cryptography applications. Reordered Normal Basis is a combination of the
type II ONB) (Sunar and
C. K. Koc., 2001). It has a characteristic of
describing the multiplication process as a stopped up formula than a matrix
operation. Any Reordered Normal Basis multiplier can be used as a type II ONB
multiplier can be restructuring of the inputs and outputs at no additional
cost. A number of architectures for multiplication using type II ONB and RNB are
in the literature (Daniel J et al; 2010). In this proposed work we mostly
focus on a serial-in-parallel out architecture, because it has low complexity
compared to parallel in serial out architecture (Bahram
Rashidi et.al.,2016). It has been shown that this
multiplier has smallest critical path delay evaluated to related designs, and
it presents an extremely usual architecture that is well suitable to a
full-custom VLSI implementation. The main
advantage of Normal Basis demonstration is squaring of the parameter can be
performed simply by cyclic shifting in its binary form (Jenn-Shyong
HORNG et al.,2009).

The uniformity of this architecture has been previously
demoralized to generate a high-speed multiplier by designing optimized,
custom-layout building blocks. In this proposed work we present additional
efficient analysis by using various building blocks, and by making use of
custom-designed flip-flops. The novel implementation can execute multiplication
15% quicker than a comparable design, although it decreases the area
utilization by 50%.

In this proposed work, section II briefly
elucidates the reviews of reordered normal basis demonstration and its
arithmetic operations. In section III, the design and execution of the
multiplier’s major building block, the XA-module, is presented. An analysis and
implementation detail of a 233-bit multiplier using XA-modules is given in
section IV. Simulation results are obtainable in section V, while a evaluation
between similar analysis and implementations is discussed in section VI.
Finally section VII includes some conclusion.

2. Reordered Normal Basis and its Arithmetic operations in F2m

2.1 Finite Field Multiplication

Finite field elements performed
arithmetic operations such as addition, multiplication, subtraction and
inversion using identity functions. Especially the value of GF (2m), where addition process
performs exclusive OR (XOR) operation and multiplication process
performs AND operation (Jenn-Shyong Horng et al.,2007; George N.
Selimis at al.,2009). Multiplication process in a finite field is
multiplication module and simplified reducing polynomial that is
used to define the value of finite field. The letter F
means finite, in that case the field is supposed to be finite(Hua Huang et al;2018)

A finite field of
GF(2m ) can be defined as the polynomial representation:

————————– (1)

Where pi
? GF(2) for 0