In handshake control circuitHalf handshake controller has 4 different

In exercise two, we were asked to implement the half handshake control circuit. Half handshake controller is an asynchronous circuit which can control the data path between two independent block and usually applied to data communication on a bus. In the process of data transmission, this protocol keeps the data path nonconducting until the data is stable at the interface of the receiving block to ensure the data is lossless. Figure 1: Half handshake control circuitHalf handshake controller has 4 different methods which will be discussed below including independent methods, unbounded methods,  csc violation methods and no redundancy methods. We were asked to simulate these 4 methods to understand the differences between them by using Workcraft.  1. Independent methodsAs the following figure indicates that signal transitions which represent requests and acknowledgements between sender and receiver are separate into two independent cyclical graphs in independent methods. It’s obvious that there is no correlation and causality between two independent  STG,  which would lead to many problems.  For instance, the receiver receives data after receives request output signal ‘ Ro ‘ goes high to ‘ 1 ‘, but request output signal ‘ Ro ‘ cannot set ‘ 1 ‘ until request input signal ‘ Ri  ‘ which is sent by sender goes high to ‘ 1 ‘. This causality is not present in the STG of independent methods. Figure 2: signal transition graphs ( STG ) for Independent methods Figure 3:  state graph ( SG ) for Independent methods 2. Unbounded methodsAs shown in figure 4, the unbounded methods modify the independent methods by inserting an arrow between ‘ Ri+ ‘ and ‘ Ro+ ‘ transitions in STG of independent methods. Sequentially it builds causality between sender and receiver. When data is stable in sending block, request input signal ‘ Ri ‘ goes high to ‘ 1 ‘ causing request output signal ‘ Ro ‘ to go to ‘ 1 ‘ and receiving block to receive data.However, this method exists unbounded problems which can be observed when the STG of this method is simulated using workcraft. In the simulation, it shows that tokens keep accumulating in the area between ‘ Ri+ ‘ and ‘ Ro+ ‘ transitions when the STG keeps running. The area is called unbounded area.  Figure 4: STG for unbounded methodsThe unbounded area of the STG shown in figure 4. The reason for this behavior is lack of  interconnection when handshake signal back from high to low.  Therefore, it needs to build another causality between receiver and sender, ensuring request input signal ‘ Ri ‘ goes to ‘ 1 ‘ after request output signal ‘ Ro ‘ goes to ‘ 0 ‘. The  STG of fixed unbounded methods is shown in figure 5.  Figure 5:   STG for fixed unbounded methods Figure 6:   SG for fixed unbounded methods 3. CSC Violation methodsThe csc violation methods is improved compared with previous methods. The figure 7 shows that there are causalities between both sides of handshake. Because there are additional arrows between Ro+ and Ao+ and between Ro- and Ao-, Ri+ will not happen until Ro- happens, Ao+ and Ri-  will not happen until Ro+ happens. Therefore there are no unbounded area in this method. Unfortunately, this method still has a problem which is not complete state coding ( csc conflict ). That means there are at least two different states have the same binary state encoding. This situation could cause a confusion about the different states which have the same binary state encoding. There is a way to fix the problem by  using the function called ” resolve csc conflicts ” in  Workcraft. The STG of corrected csc violation is shown in figure 8. The problem solved by inserting a new signal ‘ csc1 ‘, which is a internal signal in half handshake control circuit.             Figure 7: STG for uncorrected csc violation methods       Figure 8:   STG for corrected csc violation methods       As shown below in figure 9 and 10, comparing the State Graphs for STG of uncorrected csc violation and cSTG of orrected csc violation,  the SG of adding The internal signal ‘ csc1 ‘ is more complex. The states which have csc conflicts are high lighted by blue and yellow in figure 9. It is shown in figure 10 that these csc conflicts are fixed by inserting internal signal ‘ csc1 ‘ that creates an extra binary state and two signal transitions ” csc1+  and csc1-  “.  Figure 9:  SG for uncorrected csc violation methods        Figure 10:  STG for corrected csc violation methods       Using the function of Complex Gate Synthesis in Workcraft, it can generate complex gate circuits for uncorrected csc violation and corrected csc violation. As shown in figure 11 and 12, each circuit has different equations:  Complex gate circuit of uncorrected csc violation:   Complex gate circuit of corrected csc violation:          Figure 11:  complex gate circuit for uncorrected csc violation   Figure 12:  complex gate circuit for corrected csc violation 4. No Redundancy methods             Figure 13: STG for no redundancy methods           No redundancy methods is the last methods which modifies corrected csc violation methods by reducing redundant path and the extra internal signal.As shown in figure 13,no redundancy methods only has two difference comparing with the csc violation methods: 1. The arrow from Ri+ to Ao+ is removed. Because in the csc violation methods this is a redundant path which can be removed. The  path Ri+ to Ao+ has the same effect with the path Ri+ to Ro+ which can also cause Ao+. 2. The arrow from Ao+ to Ro- is added.  Figure 14:  SG for no redundancy methods As it shows in figure 14, state graph of  no redundancy methods is much more simpler than SG of csc violation methods. And the complex gate circuit of no redundancy methods is also more simpler than that of  csc violation methods,As shown in following figure. Complex gate circuit equations of no redundancy methods:      Figure 15:  complex gate circuit for no redundancy methods        Exercise 3: VME Bus Controller’ VME ‘ is short for ” VERSAmodule Eurocard “. It is a computer bus standard which is physically based on Eurocardsizes, mechanicals and connectors (DIN 41612), but uses its own signalling system 1. And ‘ VME ‘ was first created and defined by by the group of manufacturers in 1980 2. Basically VME bus controller is a type of control circuits to control the data exchange between devices and the bus.  In exercise 3, we were asked to construct  the read cycle of  VME bus controller using Workcraft. And it  is necessary to construct the STG for read cycle of  VME bus controller at the very start . The STG result is shown in the following figure:   Figure 16: STG for read cycle of VME Bus Controller Then the STG for read cycle should run some simulations to ensure there is no deadlock and unbounded area. After that the state graph for read cycle could be generated using Workcraft, which can be seen in figure 17 below.   Figure 17: SG for read cycle of VME Bus Controller  However there is a csc conflict which is high lighted by yellow. Thus it needs to be resolved by inserting a internal signal to create a new binary state and new transitions.  In Workcraft environment it can be done by executing CSC Fix, then the SG for csc fixed read cycle is recreated. The result is shown in figure 18 and 19.     Figure 18: csc fixed STG for read cycle   Figure 19: csc fixed SG for read cycle Now the STG meets the conditions for implementability: consistency, complete state coding and persistency. Therefore it is ready to begin circuit synthesis. There is a tool called Petrify in Workcraft can synthesize the circuit and can select different options to implement the circuit. The following figures are examples, one is the complex gate option, another one is technology mapping option which enable to decompose the circuit into 3-input gates.  Figure 20:  complex gate circuit for read cycle       Figure 21:  technology mapping 3-input circuit for read cycle There is another tool called MPsat in Workcraft can synthesize the circuit with technology mapping option decomposing the circuit into 3-input gates. Figure 22:  MPsat technology mapping 3-input circuit for read cycle The technology mapping enable to decompose the complex gates circuit into 3-input gates circuit and it is  important because it is more difficult to access complex gates in practical component library then 3-input gates.  The circuits synthesized above is only VME read cycle part. With the concepts of the VME read cycle implementation, it can be expand to synthesize the whole VME bus controller by combining VME read cycle with VME write cycle. The following figures are the implementation of VME bus controller:              Figure 23: STG for VME bus controller Figure 24:   csc fixed STG for VME bus controller Figure 25:   csc fixed complex gate for VME bus controller   Figure 26:   csc fixed MPsat technology mapping 3-input gates for VME bus controller .PNG          References:1 VME bus ( From Wikipedia, the free encyclopedia) : VITA Website ( FAQ on VME history and basic technology ) :